Approach to building inspection tests of digital devices on extra large integrated circuits
DOI:
https://doi.org/10.20535/2411-1031.2012.1.1.53673Abstract
Considered the problem of reducing the running in constructing a complete test for digital devices designed with using the VLSI circuits. The process of constructing a test for a given fault is reduced to finding the terminal vertices in the signals assignment tree. To reduce the iteration is proposed the focused search method wich designed to apply as the general theoretical method for finding solutions in productional type systems. Describes the results of experiments with the combinational circuits.
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