Approach to diagnosing a digital devices on a complete verification test
DOI:
https://doi.org/10.20535/2411-1031.2021.9.2.249910Keywords:
digital circuit, technical state, malfunction, verification test, diagnostic test, digital device modelAbstract
The results of research on the possibility of using a complete test to solve a current scientific and technical problem, namely, the localization of faults in a digital combination device. The purpose of this study is to increase the efficiency of diagnostic support of modern digital devices. Faults that do not convert a circuit from the category of digital circuits and distort only the functions of logic elements are considered. Such faults include faults such as fixing the values of signals in 0 and 1 at the inputs and outputs of the circuit and inputs and outputs of logic elements. The task of building a diagnostic test currently has no solution that could be recommended for practical use. A new approach to fault localization in a digital device is proposed, based on the use of a complete verification test together with deductive simulation, which reduces the number of suspected faulty technical states. The construction of a complete verification test is based on the use of methods for determining the input signals, which distinguish a pair of technical states of the digital circuit. Describes a diagnostic procedure in which the use of a full test can significantly reduce the amount of diagnostic information required to troubleshoot a digital device. The proposed procedure can be recommended for the construction of diagnostic software for digital circuits at the stages of their design and operation. A structural scheme of a software and hardware device for implementing a diagnostic procedure is also proposed. The result of the study is the conclusion that the use of a complete test significantly reduces the amount of diagnostic information and, accordingly, significantly increases the efficiency of devices of determining the technical condition of digital devices. The results of the research are demonstrated on the example of a combinational scheme C17 ISCAS. It is shown that the full verification test localizes in this scheme all constant faults of multiplicity 1.
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