Simulation method of digital circuits with faults
The simulation method of digital circuits applied to solving the problem of finding fault is not detected by the reaction scheme on the same input sequence signals (completeness check test). The method allows to build models of digital circuits that have better performance simulation speed compared with known methods. High speed simulation is achieved by bringing the process modeling operations successive logical multiplication and addition business fields, which contain all the necessary information about signals and malfunctions scheme.
Keywords: simulation method, digital circuits, malfunction.
Full Text:PDF (Русский)
Nemolochnov, O.F. (1976), Analysis and elimination of critical events in the synthesis of test signals sequences [Analiz i ustranenie kriticheskikh sostiazanii signalov pri sinteze testovykh posledovatelnostei], Automation and Remote Control, № 11, pp. 173-181.
Еiсhеlbеrgеr, Е.B. (1965), Hаzаrd dеtесtiоn in соmbinаtiоnаl аnd sеquеntiаl switсhing сirсuits, IBМ Jоurnаl Rеsеаrсh аnd Dеvеlорmеnt, Vol. 9, № 3, рp. 90-99.
Birger, A.G. (1981), The simulation method of discrete devices [Metod modelirovaniia diskretnykh ustroistv], Automation and Remote Control, № 1, pp.138-144.
Sapozhnikov, V.V., Sapozhnikov, Vl.V. (1978), Relations between faults in combinational logic circuits [Ob otnosheniiakh mezhdu neispravnostiami v kombinatcionnykh logicheskikh skhemakh], Avtomatika And Remote Control, № 1, pp.167-171.
This work is licensed under a Creative Commons Attribution 4.0 International License.
ISSN 2411-1031 (Print), ISSN 2518-1033 (Online)